1. Field of the Invention
The present invention relates to a semiconductor device, particularly relates to a semiconductor device comprising a logic block.
2. Description of the Related Art
Demands for more compact, thinner and lighter portable electronic devices, such as a digital video camera, a digital cellular phone and a notebook computer, only get stronger. To respond thereto, seven tenths of reduction has been realized in three years in a recent VLSI and other semiconductor devices.
Such a reduction of semiconductor devices has been attained by an improvement of production techniques, such as a lithography technique and etching technique, and development of processing techniques to attain the minimum processing dimension of 90 nm has been pursued.
In production techniques before the generation of 90 nm, variation of processing dimensions of gate electrodes of MOS transistors was ±5 to 10% or so with respect to a targeted dimension including a lithography technique and etching technique.
However, in currently pursued production techniques of the 90 nm generation, variation of the processing dimensions is ±10 to 15% or so, and the variation of the processing dimensions is liable to become larger with the pursuance of miniaturization in the 90 nm generation or later. As explained above, in a semiconductor device, when variation of processing dimensions of gate electrodes becomes large, unevenness of DC components of a power consumption becomes large, so that it becomes difficult to attain a higher speed and a lower power consumption at a time.
Particularly, in a semiconductor device including a logic block, normally, a region for forming a gate electrode and a vacant region for not forming a gate electrode of a MOS transistor composing a logic circuit exist in a logic block, and a pattern density in the logic block is uneven.
Therefore, due to a light proximity effect at exposure and a micro-loading effect at etching in a step for performing pattern processing on a gate electrode, it is liable that a difference arises between processing dimensions of the gate electrode in a nondense region and processing dimensions in a dense region, which leads to wider variation of processing dimensions.
Accordingly, when designing a semiconductor device including a logic block of the 90 nm generation or later, it is particularly necessary that variation of processing dimensions of a gate electrode is suppressed.
A technique of forming a dummy electrode spreading allover a vacant region in the logic block to suppress variation of processing dimensions has been known, however, suppression of the variation of processing dimensions thereby was insufficient.
On the other hand, it is known that, along with miniaturization, and a larger scale and a higher frequency of a circuit in a semiconductor device of the 90 nm generation or later, a power source noise on a chip increases exponentially.
Since the increase of a power source noise causes an erroneous operation of the circuit, a remedy has been particularly demanded to suppress the power source noise in a semiconductor device of the 90 nm generation or later.